The present disclosure relates to a semiconductor storage device having a dual-port (DP) static random access memory (SRAM) cell.
The dual-port SRAM cell is a memory cell in which two data access requests can be made within one cycle. As shown in FIG. 7A, a typical dual-port SRAM cell is connected to two word lines and two pairs of bit lines, and is comprised of eight transistors. In contrast, as shown in FIG. 7B, a typical one-port SRAM cell is connected to one word line and one pair of bit lines, and is comprised of six transistors. Compared with this one-port SRAM cell, the dual-port SRAM cell is larger in number of the transistors and size of the transistors. This increases the cell area and current consumption per bit.
To solve the problem of such a dual-port SRAM cell, Jason Stinson et al., “A 1.5 GHz Third Generation Itanium Processor”, IEEE, ISSCC (International Solid-State Circuits Conference) 2003 discloses a configuration of a dual-port SRAM cell comprised of six transistors, which is the same as those in a one-port SRAM cell. In this circuit configuration, a word line of the one-port SRAM is separated into two word lines, so that the separated two word lines respectively drive two access transistors. Thus, the SRAM cell comprised of six transistors allows simultaneous access to two ports. This can reduce the cell area and the current consumption.